A non-volatile memory device such as a flash memory device continuously holds data until it is erased. Therefore, unlike a volatile memory device such as a normal DRAM, the non-volatile memory device does not require refresh-related circuitry and can save power consumption.
However, the non-volatile memory device needs a high voltage for writing/erasing data and an extra storage for holding data. This complicates the structure and forming processes. For example, the non-volatile memory device may additionally need a charge storage for reliably preserving data and a voltage drop resistor for driving high and low voltage areas from a single power source.
Based upon a structure, memory cells of the non-volatile memory device type are classified into a floating gate type memory cell and a floating trap-type memory cell. In the floating trap-type memory cell, programming can be carried out by storing a charge in a trap formed in a non-conducive charge storage layer between a gate electrode and a semiconductor substrate. To form a floating trap, a tunneling insulating layer and a blocking insulating layer are formed on/beneath a silicon nitride layer acting as a charge storage layer.
FIG. 1 is a cross-sectional view showing a typical SONOS (silicon oxide nitride oxide semiconductor) structure of the floating trap-type memory device. A memory cell has a gate pattern and impurity diffusion layers. A gate pattern is formed by sequentially stacking a tunneling insulating layer 20, a charge storage layer 22, a blocking insulating layer 24, and a gate electrode 27 on an active region of a semiconductor substrate 10. An impurity diffusion layer 28 is formed in an active region on both sides of the gate pattern. Typically, the tunneling insulating layer 20 is made of thermal oxide and the charge storage layer 22 is made of silicon nitride.
In a non-volatile semiconductor memory device having a floating gate, a gate insulating layer of a memory cell conventionally has the same thickness as a gate insulating layer for forming a transistor of a low-voltage area in a peripheral circuit region. However, a tunneling insulating layer of the floating trap-type memory cell conventionally is different, in suitable thickness, from a gate insulating layer for forming a transistor of a lower voltage area in a peripheral circuit region. Therefore, the process for fabricating a non-volatile semiconductor device having the floating trap-type memory cell is more complex than the process for fabricating a non-volatile semiconductor device having the floating gate-type memory cell.